1. Field of the Invention
This invention relates generally to cache architectures for processing systems having store in caches which can globally address a main memory, and more particularly to dynamically partition the globally addressable caches while retaining all current data.
2. Description of the Prior Art
Multi-processor data processing systems use multi-level caching to enhance system performance. A typical configuration includes first level caches dedicated to each processor, a second level cache shared by the processors, and a third level main memory shared by the processors. One variation uses a second level cache that maps to all of the addressable memory (i.e. is globally addressable) and can retain modified data that is different than what is reflected by the main memory (i.e. store in or post store).
U.S. Pat. No. 5,265,232 to Gannon et al. entitled, COHERENCE CONTROL BY DATA INVALIDATION IN SELECTED PROCESSOR CACHES WITHOUT BROADCASTING TO PROCESSOR CACHES NOT HAVING THE DATA, illustrates a centralized second level cache approach.
U.S. Pat. No. 5,136,700 to Thacker, entitled, APPARATUS AND METHOD FOR REDUCING INTERFERENCE IN TWO-LEVEL CACHE MEMORIES, illustrates a multiprocessor computer system with a number of processors coupled to a main memory by a shared memory bus, with one or more of the processors having a two level direct mapped cache memory. A special table is provided in the second cache which stores a pointer for each line in the first cache array which uses a look-up circuit to compare the pointer with the memory to determine, if a match exists, that the cache was updated. This system operates only upon data currently in use by a processor.
U.S. Pat. No. 4,713,751 to Dutton et al, entitled, MASKING COMMANDS FOR A SECOND PROCESSOR WHEN A FIRST PROCESSOR REQUIRES A FLUSHING OPERATION IN A Multi-processing SYSTEM, illustrates a masking circuit which senses the existence and type of commands stored in the command status registers associated with the system processors. Masking begins if it is determined that information needed by one processor is located in the cache memory of another processor and is to be flushed to the main processor. The masking circuit masks the command present in the command status register until after the information has been flushed from the cache to the main memory. This apparatus also operates only upon data immediately in use by a processor.
None of these provide separate second level cache memories for a number of processors which permit transferring data pertaining to one set of processors from one second level cache to the other prior to isolating the second level cache memories. It would be desirable if all current operand data pertaining to a remote system in the second-level caches of such systems could be transferred to the other second-level cache before powering down, or otherwise isolating the systems.